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风暴前夕:Intel/IBM 22/15nm制程要害制造手艺前瞻

宣布时间:2010年01月11日 13:01    宣布者:phoenixmy
要害词: IBM , Intel , 风暴 , 要害 , 制程
半导体特点尺寸正在向22/15nm的品级赓续镌汰,传统的平面型晶体管还能知足请求吗?有关这个效果,业界曾经议论辩说了良久。现在,决议半导系统体例造手艺生长偏向的历史拐点行将到来,虽然IBM和Intel两年夜阵营在生长要领上会有各自不合的气焰气焰和蹊径,但双方均已亮相当在15nm级别制程启用全耗尽型晶体管(FD:Fully Depleted)手艺简直已成定局,同时他们也都曾经在认真推敲下一步要不要将垂直型晶体管制造手艺如三门晶体管,finFET等投入适用。

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据Intel的制程手艺司理Mark Bohr体现,Intel 对部门耗尽型(PDartliy Depleted)CMOS手艺能否一连沿用到15nm制程节点以为“异常消极”。但他同时体现,虽然只需SOI手艺才可以在生涯传统平面晶体管结构的条件下应用FD手艺;然则体硅制程也着实不是无可救药,接纳三门或许FinFET等平面晶体管结构手艺,便可以在体硅或许SOI上知足要害尺寸进一步镌汰的需求,一样也能够或许制造出FD MOSFET

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Gartner的剖析师Dean Freeman则体现,现在半导体业界所面临的情形与1980年月异常类似,其时业界为了挣脱面临的生长瓶颈,泉源徐徐接纳CMOS手艺来制造内存和逻辑芯片,从而开创了半导体业界的新纪元。

栅极宽度赓续减小所带来的负面效应愈来愈显着。首先,为了扫除短通道效应,人们不克不及不向沟道中搀杂磷,硼等杂质元素,这便招致管子门限电压Vt的上升,同时还降低了沟道中电子运动的速率,组成管子速率的降低。而且用来向沟道中搀杂杂质的离子注入工艺也存在很难控制的效果,很容易组成管子门限电压过年夜等不良效果。

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其次,传统的SiGe PMOS硅应变手艺也泉源面临瓶颈,在32nm制程节点中,漏源南北极中搀杂的锗元素含量曾经占到了40%左右,很难再为沟道原子供应更高等其他应变.

其三,栅极氧化物的厚度方面也将泛起生长瓶颈效果.IBM研发中央的高管Bruce Doris体现,栅极氧化物厚度减薄的速率曾经跟不上栅极宽度镌汰的措施.

其它一些平面型晶体管所面临的效果也将愈来愈难处置赏罚赏罚.使命电压的赓续降低,使芯片的功耗控制变得愈来愈艰辛;而且要害尺寸的镌汰还会招致漏/源极电阻的赓续增年夜.

那么业界有甚么战略来应对这些寻衅呢?

Intel的战略:22nm仍接纳传统手艺,15nm能够转向三门结构

据Intel体现,不才一代22nm制程产物中,他们仍将一毗邻纳传统基于体硅的平面型晶体管结构(此前曾有传言称 Intel会在22nm制程中转向平面结构的三门晶体管手艺),他们妄图于2011岁尾正式推出22nm制程手艺。而在今年的9月份,Intel曾经展示过一款接纳22nm制程手艺制造的SRAM芯片,这类芯片的存储密度为364Mb,内含29亿个晶体管,而且接纳了Intel第三代gate-last HKMG制程手艺,门极绝缘层和金属栅极的主要部门在制造工序的最后几个工步制组成型,避开前面的高温退火工步(45/32nm中应用的前代手艺则只需金属栅极才在最后几个工步制组成型)。

至于15nm制程节点,Bohr体现,Intel现在正在推敲在15nm制程节点上要接纳哪些新的制程手艺以知足请求,他以为:“全耗尽手艺对降低芯片的功耗异常有用。”不外 Intel现在也在推敲除此以外的多种可行性妄图,好比是转向三门晶体管手艺(三门手艺着实与IBM的双门finFET同属finFET型晶体管,但由于对手将其双门手艺命名为finFET,是以Intel便凭证自己的finFET手艺特点将其命名为三门手艺),或许是转向全耗尽+平面型晶体管手艺等等。据Bohr体现,Intel会在六个月以内就15nm制程节点将接纳哪一种新手艺做出决议。

此前据Intel前手艺司理Scott Thompson预计,Intel事实会选择接纳三门结构晶体管制程,而其它的厂商则会由于FinFET结构的制程工艺严重年夜性而对FinFET望而生畏。Scott Thompson现在的职位是在佛罗里达年夜学任教。

按Intel的性格,他们一直对SOI工艺保持驯服的态度。不外Bohr体现:“我们要找的是一种性价比最高的妄图,岂论是SOI或许其它的甚么手艺,只需某种手艺能够带来特此外性能提升或较低的功耗,那么我们就会接纳这些手艺。”

IBM阵营的战略:22nm有能够转向FD-ETSOI,15nm能够启用finFET结构

IBM阵营方面,与Intel不合,虽然有能够后延到15nm制程节点时间段,但IBM公司曾经泉源推敲要在22nm制程节点便泉源应用FD-SOI手艺。IBM公司12月份曾经展示了一种基于ETSOI(extremely thin SOI:超薄SOI)的FD-ETSOI工艺。这类工艺依然基于传统的平面型晶体管结构,不外这类工艺的SOI层厚度则异常薄,这样便可以接纳全耗尽工艺,能够显着减小短通道效应(SCE)的影响。

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ETSOI手艺能将SOI层的厚度镌汰到极低的水平,应用这类手艺以后,22nm制程中的SOI层的厚度唯一6.3nm,而传统的SOI层厚度通常在 20nm以上,生长到15nm制程,SOI层的厚度还可以进一步被镌汰到5nm左右。据IBM体现,虽然由Soitec公司供应,能用于制造ETSOI产物的SOI晶圆数目仍很是无限,但他们曾经可以把这类SOI层的厚度误差控制在±5 ?左右.

不外ETSOI手艺也有其难点,由于SOI层的厚度极薄,是以很容易遭到破损。而且为了防止对SOI层组成破损,在制造漏/源极时不克不及接纳传统破损性较强的离子注入手艺,必须接纳就地搀杂手艺(in-situ doping)。“我们接纳的是不会风险ETSOI层确就地搀杂手艺。我们首先天生栅极隔离层,然后在漏源区用内在手艺群集生长出漏/源极,组成内在层(图中的epi)并在漏/源极的生长历程当中同时就地搀杂所需的杂质元素,然后我们会对晶体管阻拦加热处置赏罚赏罚,令漏源极中的搀杂原子向沟道偏向疏散,构身疏散层(图中的ext)。而加热处置赏罚赏罚历程当中我们应用的尖峰退火手艺(spike anneal )则不会对ETSOI层的结构组成不须要的风险。”

隶属IBM手艺同盟的GobalFoundries的手艺开发司理John Pellerin也体现这类FD-ETSOI手艺很快便会付诸适用,不外他体现:“然则我们现在很难说详细甚么时间会转向这类手艺。”Pellerin体现,FD-SOI手艺从应用结构上看与现有的PD-SOI手艺异常相近,“我们只须要把SOI层的厚度变薄,并想措施处置赏罚赏罚ETSOI带来的一些效果便可,其它的部门则和传统的制造工艺基内幕同。”虽然ETSOI手艺仍有许多其他的效果须要处置赏罚赏罚,好比若何减漂亮件的寄生电阻等等。

IBM的下一步:finFET

另据Pellerin体现,在ETSOI手艺生长的下一步很能够会泉源启用finFET平面型晶体管结构,二者的关系就像之前我们从部门搀杂型SOI(PD-SOI)手艺过渡到FD-SOI那样。“我看不出来ETSOI和finFET两种手艺之间存在甚么抵触的地方,而且接纳平面型结构ETSOI手艺所能到达的晶体管密度总会泛起生长瓶颈,而finFET则可以处置赏罚赏罚这类效果。”

2009年,IBM公司增添了用于实验finFET效能的晶圆样片数目,据他们体现,finFET手艺所带来的性能提升“令人异常知足。”不外 finFET与平面型晶体管之间各有优劣。“平面型晶体管结构着实不须要对传统的工艺阻拦太多刷新,之前30年来人们所应用的许多手艺都可以应用在平面型结构的ETSOI里,而要进一步升级为finFET结构,所须要的制造工艺则严重年夜许多,这类手艺对光刻和蚀刻手艺提出了很高的请求。”

ETSOI赞助手艺:SiC硅应变手艺

在22nm节点,看起来至少1家以上的年夜型厂商会接纳向NMOS管的漏源区搀杂碳原子的措施来为沟道施加拉伸应力,以组成应变硅。IBM在形貌自己的 FD-ETSOI工艺时曾经提到,他们会在群集NMOS管的漏源极时向极内搀杂碳杂质。而且另外一家IBM工艺手艺同盟的成员Applied Materials公司也划分在去年的IEDM和今年的Semicon会展上两次强调了这类SiC硅应变手艺的可行性。

那么外界对SiC 手艺的评价若何呢?据GlobalFoundries公司的Pellerin体现:“我们正在关注SiC硅应变手艺,而且正在推敲在我们的22nm及更高等别制程中应用这项手艺。”在现在的工艺尺寸条件情形下,要想很好地控制漏源区的离子注入历程将是一项异常严重年夜的义务,而在IBM的FD-ETSOI工艺中,NMOS中应用的SiC硅应变手艺则与PMOS中的SiGe硅应变手艺一样是接纳内在群集完成的,不用再为若何控制离子注入而担忧。他并体现:“怎样在NMOS管中应用硅应变手艺将是另外一个刷新晶体管性能的要害手艺。”

相比之下,Intel的Bohr则完全改变了他对SiC硅应变手艺的态度,他之前曾经体现 Intel更偏向于应用SiC硅应变手艺,不外比来他在IEDM2009聚会聚会会议中吸收采访时则体现他不愿意就Intel在SiC硅应变手艺方面取得的停留揭晓任何议论。而会上代表Intel做有关Intel 32nm制程手艺演讲的Paul Packan则在演讲后回复记者提问的环节没有剖析一名记者提出的有关SiC硅应变手艺在32nm制程NMOS结构中应用状态的效果。

小结:Intel与IBM:你走你的阳光道,我过我的阳关道

Gartner 的剖析师Freeman体现,他以为Intel和AMD会一连走自己的老路,Intel不太能够会应用SOI手艺,而IBM则会一连将SOI发扬光年夜。他以为Intel假定接纳三门晶体管手艺,“便可以绕开SOI,是以Intel未必会转向SOI。”他并体现:“Intel会尽能够地延伸体硅制程的寿命,而IBM则会尽快转向全耗尽型SOI手艺。”他还以为未来Soitec和信越化学公司(SEH, Tokyo)将具有向IBM供应切合对方须要的ETSOI晶圆的才干(现在IBM须要在厂内对ETSOI硅层阻拦处置赏罚赏罚)。

其它要害手艺:

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除以上所述的行将投入应用的手艺以外,用于制造场效应管沟道的半导体质料下一步也有能够会发生变换。在去年的IEDM聚会聚会会议上,斯坦福年夜学的教授 Krishna Saraswat曾体现,当沟道宽度降至10nm左右时,必须接纳新质料来制造沟道。据他预计,业界将首先开发出NMOS管应用III-V族元素构建沟道,PMOS管应用锗元素构建沟道的手艺,然后再向PMOS/NMOS统一接纳III- V族元素制造沟道的偏向生长。转向应用III-V族元素将年夜年夜减漂亮件的使命电压和管子的能耗,可将使命电压减小至0.5V。不久之前,Intel便简介了他们在应用这类手艺制造的QWFET场效应管方面取得的新停留,其时他们向这类晶体管结构中引入了High-K栅极氧化物层。

除此以外,IBM则在TSV硅通孔互连手艺和3D堆叠封装手艺方面取得了较年夜的停留。

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原文:semiconductor
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老郭 揭晓于 2010-1-11 16:46:12
CMOS Transitions to 22 and 15 nm

Scaling beyond the 22 nm node is likely to require fully depleted CMOS, either on SOI or bulk wafers. TSV 3-D interconnects and SiC stressors also appear likely to be implemented, while the jury is still out on when vertical finFETs and III-V devices will be widely implemented.


David Lammers, News Editor -- Semiconductor International, 1/1/2010

Technologists have long debated how far plain-vanilla planar CMOS transistors on bulk silicon wafers could be scaled. Now, the transition to new paradigms appears to be underway, with fully depleted CMOS almost definitely on the 15 nm roadmaps at IBM and Intel, with some form of vertical transistors being seriously considered as well.

Mark Bohr, Intel's director of process architecture and integration, said he and his Intel colleagues are "pretty pessimistic that partially depleted (PD) CMOS will extend to the 15 nm node." A planar, fully depleted (FD) technology could only be constructed on a silicon-on-insulator (SOI) substrate, Bohr said, but a tri-gate or finFET device could be created on either bulk or SOI wafers.

Gartner analyst Dean Freeman likens the current period to the early to mid-1980s, when first memory and then logic transitioned to CMOS. "The NPN transistor gave the CPU vendors a new lease on life. I think we are at a point like that again. But the question is out there: How do we keep innovating?"

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1. Drive currents have been slowed by higher threshold voltages and slowed gate length scaling. (Source: Intel, 2009 IEDM)

Changes — whatever they may be — are coming because for the last generation or two, scaling the gate length (Lg) has resulted in reverse scaling (Fig. 1).1 To avoid short channel effects (SCE), more phosphorus and boron are being doped into the channel, raising threshold voltages and slowing transistors speeds. Random dopant fluctuations (RDF), in which the number of dopants in the channel vary as a function of the halo implantation, can have a large influence on the Vt, hurting performance and cutting overall yield.

Strain also faces limits. More germanium can be added to the SiGe stressors — from the ~40% germanium level used at the 32 nm node — but there is less room for the material to create the strain.

While IBM, Intel and others are thinning the gate dielectric with high-k materials, the gate dielectric "is not thinning as fast as we need it to in order to make an appreciable improvement in gate length scaling," said Bruce Doris, manager of advanced device integration at IBM's Albany, N.Y., R&D center. Other knobs are getting harder to turn as well. Operating voltages are leveling off, making it more difficult to reduce power consumption. Making the junctions shallower is causing the source/drain resistance to increase.

What to do? At 22 nm, Intel will stay on a bulk technology, Bohr said. Intel is on track to introduce its 22 nm MPUs at the end of 2011. The Intel 22 nm test chip (Fig. 2) with SRAM arrays and logic peripheral circuits was introduced in September with a 364 Mb array size and 2.9 billion transistors. It includes a third-generation gate-last high-k/metal gate process that deposits both the dielectric and the metals at the end of the process.

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2. Intel's 22 nm test chip has 2.9 billion transistors. (Source: Intel)

Thus far, performance gains from Intel's strain techniques — including the PMOS strain added from the replacement gate, or gate last, method of depositing high-k/metal gates — have more than compensated for the speed degradation coming from the deleterious effects of channel doping. Going forward, however, Bohr said "further invention" will be needed, beyond pitch and gate length scaling.

Now working on pathfinding technologies for the 15 nm generation, Bohr said, "Fully depleted technologies have inherent low-power advantages." Intel is exploring a range of options, Bohr said, including tri-gate devices and fully depleted planar technologies. Intel has a decision to make in about six months, when it will lock in the process architecture for its 15 nm technology.

(Scott Thompson, a former Intel technology manager who now teaches at the University of Florida at Gainesville, believes Intel will adopt a tri-gate structure at some point, while the rest of the industry will shy away from the manufacturing challenges of finFETs.)

Historically, Intel has not been positive about SOI for partially depleted, planar CMOS devices. "We look for value," Bohr said. "Whether it is SOI or an extra metal layer, we do it if it gives us extra performance or lower power."  

John Pellerin, director of technology development for GobalFoundries, also said fully depleted CMOS is coming, though he said it is "difficult to draw discrete lines in the roadmap where such transitions occur."

As a foundry that counts Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) as its first customer, GlobalFoundries will support AMD and others with an SOI roadmap, while advancing bulk for other customers. Because so many companies are pooling R&D resources at the Fishkill Alliance, Pellerin said, "We do have the benefit of pursuing multiple architectures in parallel. Bulk is the incumbent for many applications, while for some high-performance sectors, PD-SOI is the incumbent. When those are dethroned is difficult to predict. What we do is look at novel architectures while at the same time raising the bar of the incumbents. That makes it more challenging for the newcomers."

Partially depleted or conventional bulk transistors "become quite difficult" as scaling proceeds, Pellerin said. "In order to get the short channel characteristics required, certainly fully depleted device architectures — be they vertical devices like finFETs or planar SOI — allow you to take that challenge of channel control out of the equation. That's the enticement: not stuffing a lot of doping in the channel to control the short channel effect."

The ability to get a consistent amount of doping in the channel is becoming difficult to manage. "That's where variation gets difficult," Pellerin said, "and where a fully depleted type of architecture starts to look very attractive."

IBM, for its flagship MPU process technology, is considering making a move to fully depleted technologies as early as the 22 nm node, though it is more likely to come at 15 nm. Ghavam Shahidi, director of silicon technology at the T.J. Watson Research Center (Yorktown Heights, N.Y.), said IBM is developing fully depleted transistors, using planar structures on extremely thin SOI (ETSOI) wafers.2 ETSOI results in a thin silicon body, which reduces short channel effect (SCE) problems that stem from scaling the extensions to less than the depletion width.

"Thin-body devices make the thinning of the extensions simpler, and they reduce the [gate-induced drain leakage] and Vt variations. The undoped body has much lower leakage and dopant variations," Shahidi said.

PD-SOI involves learning to deal with the SOI history effect, which affects the Vt level and complicates design somewhat. With FD-SOI, there is no history effect, which makes FD-SOI design much simpler for smaller companies.

The ETSOI technology incorporates several process innovations, including in situ doped epitaxial (implant-free) deposition of the source/drain and extension regions, and a faceted raised source/drain architecture, said Kangguo Cheng, lead engineer on the 22 nm device integration team at IBM's Albany R&D center.

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3. Extremely thin SOI technology requires a thin silicon layer, and small thickness variations. (Source: IBM)

ETSOI requires an extremely thin body, with the critical silicon layer on the SOI wafer in the 6.3 nm range for the 22 nm generation, and even thinner, ~5 nm, for 15 nm devices (Fig. 3). Doris said most of the 300 mm SOI wafers delivered to IBM from Soitec (Bernin, France) have an acceptable silicon thickness variation of ±5 Å, although the shipments from Soitec have been in limited quantities thus far.

ETSOI processing must be done carefully beacuse the thin silicon layer can recrystallize. "The silicon is so thin," Cheng said, "once you destroy the top silicon layer there is nothing left to recover." In situ doping, rather than implantation, is required, also to avoid material destruction.3 "We do in situ doping, which is non-destructive. We form the spacer, and need to leave the S/D epitaxial growth with the in situ dopants. After that, we heat up the wafer so dopants in the S/D can move toward the channel." A spike anneal does not destroy the silicon structure, he explained.

While the ETSOI team is aiming for introduction at the 22 nm node ("All the ducks seem to be lining up," Doris said) the power of incumbency may keep IBM on partially depleted SOI until the 15 nm node.

Pellerin, who manages the GlobalFoundries technology development team at Fishkill, said FD-SOI looks topographically similar to PD-SOI. "We are just dealing with a very thin body. It shares the processes we've grown accustomed to, and is good for channel characteristics." There is still the series resistance problem, and work is required to connect the source and drain to the channel. A raised S/D and other types of approaches have to be considered. "One challenge is: How do I reduce that parasitic resistance of that device?" Pellerin said.

Gartner analyst Freeman said he believes that Intel and IBM will stick by their traditional guns, with Intel shying away from SOI substrates as long as possible and IBM pushing SOI as hard as it can. The Intel tri-gate structure, Freeman noted, "doesn't have to use SOI, because the area gets so small. There is still leakage at the substrate, but it is not a given that Intel has to go to SOI."

Freeman's prediction is that "Intel will stretch bulk wafers as long as it can." IBM, on the other hand, will move as fast as is practical to fully depleted SOI. Both Soitec and Shin-Etsu Handotai (SEH, Tokyo) will be able to supply ETSOI wafers with the required specs, he said.

FinFETs remain enticing

FinFETs are another major path of investigation.3 Pellerin said ETSOI and finFETs also should be considered as a continuum, just as PD- and FD-SOI are. "I don't see one excluding the other. Both share some common advantages, and they also have their own unique set of integration challenges. To get to the transistor densities we will need, planar can only be shrunk so much. When we have to go to a finFET, it opens the door to an ability to achieve those transistor densities because we can pack vertical devices a lot closer together. FinFETs do have that additional knob of transistor density, to levels that planar would have difficulty in achieving."

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4. FinFETs offer scaling advantages, but present manufacturing issues. (Source: IBM)

FinFETs and tri-gate structures both involve "extra process complexity," Bohr said, but there is a payoff. Tri-gate structures have challenges with parasitic resistance and capacitance, but Bohr said Intel's tri-gate devices are demonstrating "better performance than any other published tri-gate or FinFET device."

IBM doubled the number of R&D wafers on its finFET program in 2009 (Fig. 4), and the finFET effort is getting "really nice results," Doris said. "There are pros and cons of each one." A planar structure "is so comforting because it keeps the design style people are used to," he said. Although the width can be varied on planar transistors, with finFETs, "you have to add them up. There is no arbitrary width, so you quantize it and make more fins."

Doris added, "I believe most people in the industry would agree that finFET processing is more difficult. Lithography is a huge challenge, though people can overcome that with sidewall image transfer."

Etching the gate is another challenge. The gate wraps around the fin, making it difficult to characterize the profile of the gate. For there to be acceptable transistor characteristics, "the gate has to be as straight as possible," Doris said.
In planar structures the gates lie in one plane, but "in finFETs, the gates are traversing the channel up and down all over your wafer. That poses some fundamental questions and approaches to how you integrate all the processes together to make that device," Doris said.

When the gate wraps around the fin, it is difficult to optimize. "Much of the processing that the industry has used for the past 30 years can still be used on planar ETSOI," Doris said. "This industry tends to take very small steps. That's how we got to where we are. And that's why doing something fundamentally different like finFETs, at the same level of complexity, is hard to fathom in the near future."  

Pellerin said he has spoken to design customers about how prominent the design challenges to finFETs may be, in particular the "discretized device Ws."

GlobalFoundries is targeting the 20 largest foundry customers, and they have not cited transistor width as a "showstopper or even a roadblock," Pellerin said. "We can offer multiple fins. Device designers don't use width as an analog kind of knob anyway. So while design with finFETs has been talked about, it is not panning out to be an issue at all."

Freeman said although most companies are leery of finFETs because of the lithography and etching challenges of the vertical structures, "in one sense the epitaxial raised source/drain structures already are vertical in nature."

SiC: yes or no?

At 22 nm, it appears likely that one or more of the leaders will use the smaller-than-silicon carbon atoms to exert a tensile (pulling) stress on the silicon NMOS channel. The epitaxial structures on IBM's ETSOI process described at the recent International Electron Devices Meeting (IEDM), for example, use in situ doping to add SiC as a stressor on the NMOS devices. At the 2008 IEDM, and again at the 2009 Semicon West, the Fishkill Alliance partners, including Applied Materials, said they had demonstrated that SiC strain is workable.

But has anyone committed to SiC? Pellerin said SiC is "an element we are looking at and considering for our 22 and below device architecture." Implanting the source/drain regions is becoming more complicated, and the SiC stressors are epitaxially grown, much like the SiGe strain regions on the pFETs. "Strain to the NMOS channel becomes another knob with which to improve performance," Pellerin said.

Bohr has changed his tune somewhat on SiC stressors. In the past, he said Intel was leaning against SiC, but in an interview at the 2009 IEDM he said he didn't want to comment on the current status of SiC at Intel. Paul Packan, who presented Intel's 32 nm transistors at IEDM, also didn't reply to a question from the audience about SiC on the 32 nm NMOS devices.

TSVs: Not only for memory

Through-silicon vias (TSVs) and 3-D chip stacking are another technology that appears to be on the cusp of volume production. Already, IBM offers a fast SOI-based embedded DRAM capability, used on the Power 7 microprocessors and also offered to its foundry customers. TSV interconnected memory could be another weapon in IBM's unique technology arsenal of SOI, embedded SOI DRAM and, soon, TSV interconnects.

Pellerin said TSVs will "definitely play a role" going forward, adding, "Embedded dense memory is an equally viable option and has a strong role to play. 3-D with TSVs is another approach to achieving that. And we shouldn't limit it to a logic chip mated to a memory. With TSVs, customers can really do heterogeneous types of integration that go beyond memory, enabling high-form-factor, high-function handheld devices. They can gain a lot of leverage in terms of what they can do in a small amount of space with heterogeneous die stacking using 3-D and TSVs."

A role for heterogenous devices?

By heterogeneous, Pellerin was referring to connecting logic with, say, optoelectronic or other devices that require a different material technology. Another meaning to the word heterogeneous is the use of a III-V transistor on the NMOS and a germanium transistor on the PMOS, for example. At the 2009 IEDM evening panel discussion, Krishna Saraswat, a professor at Stanford University, predicted that around the 10 nm channel length the industry will need to shift to new channel materials. Ideally, the industry will develop a decent III-V PMOS transistor to complement a III-V NMOS transistor, he said, a combination that would have "much lower power" consumption than silicon devices. "A III-V [NMOS] and germanium PMOS would be able to come in earlier that an all III-V solution, representing a good compromise," Saraswat said.

Going forward, controlling power is the main challenge, said Raj Jammy, director of the front-end program at Sematech (Austin, Texas). "We need true high-performance devices with low power too. There is a blending or convergence going on," Jammy said, adding, "The beauty is that once we get to III-V devices, we can get to half of the operating voltages used today — to 0.5 V."

Jammy led a Sematech workshop preceding IEDM on heterogeneous devices that combine a III-V (InGaAs is the most likely material set) device on the nFET, and perhaps a germanium channel on the pFET.4 The heterogeneous approach uses epitaxial techniques, depositing a III-V and germanium on a 300 mm wafer only in the critical circuits.

For many university researchers, III-V-based devices are well-suited to the blending that may be needed. "III-Vs have made rapid progress in the last six months, more than many industry people realize," said T.P. Ma, a professor at Yale University.

Some researchers, such as Akira Toriumi, now a University of Tokyo professor after a career at Toshiba Corp., argue that germanium channels can be used for both pFET and nFET devices.5 Jammy cautioned that "a germanium nFET is not easy, because of high contact resistance and high interface states."

5.jpg
5. Thus far, III-V devices have high mobility but face density issues. (Source: Intel)

Robert Chau, director of transistor research and nanotechnology at Intel's Technology and Manufacturing Group in Hillsboro, Ore., said Intel has develop III-V n-channel devices (Fig. 5) with "very, very high mobility, significant gains in effective velocity and drain current. However, the footprint scalability remains an unknown."6

Professor Dimitri Antoniadis, who heads up the Marco Center and device research at the Massachusetts Institute of Technology (MIT, Cambridge, Mass.), said III-V transistors "will help on the speed and power vectors; the density vector is tricky. They may not help on gate length scaling; there is a lot more work that needs to be done on scalability."

Thomas Skotnicki, a research manager at STMicroelectronics (Geneva), raised doubts about whether III-V devices will ever be introduced into mainstream ICs. "Silicon gives us the speed we need. At best, III-Vs will be limited to high-speed paths. The high-mobility materials might be introduced locally to improve variability, which is a key problem."

References

1. P. Packan et al., "High Performance 32 nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors," 2009 IEDM Proc., p. 659.
2. G. Shahidi, "Device Architecture: Ultimate Planar CMOS Limit and Sub- 32nm Device Options," 2009 IEDM Short Course, p. 25.
3. K. Cheng et al., "Extremely Thin SOI (ETSOI) CMOS With Record Low Variability for Low Power System-on-Chip Applications," 2009 Proc., p. 49.
4. D. Lammers, "Silicon May Prevail Despite Power Fears," Semiconductor.net, Dec. 7, 2009.
5. C.H. Lee et al., "Record-High Electron Mobility in Ge n-MOSFETs Exceeding Si Universality," 2009 IEDM Proc., p. 457.
6. G. Dewey et al., "Logic Performance Evaluation and Transport Physics of Schottky-Gate III-V Compound Semiconductor Quantum Well Field Effect Transistors for Power Supply Voltages (VCC) Ranging From 0.5V to 1.0V," 2009 IEDM Proc., p. 487.
老郭 揭晓于 2010-1-11 16:53:13
小菜农找的译文和原文不不合呀
phoenixmy 揭晓于 2010-1-11 17:26:40
预计是cnbeta翻译的不行。。。
Netjob 揭晓于 2010-1-12 12:53:18
不拉更的器械,  与我们和干?
Netjob 揭晓于 2010-1-12 12:53:29
不拉更的器械,  与我们和干?
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